| 摘要 |
PURPOSE:To execute a DMA transfer to a basic bus without waiting time after the preceding transfer is terminated by invalidating a time-out detecting function held by an input output controller itself connected through an extension bus only during the DMA transfer. CONSTITUTION:The title system is a computer system equipped with a bus system extension device connected with a central processing unit through a basic bus B1 and an input output controller connected with the bus extension device through an extension bus B2 and the bus system extension device is equipped with a time-out detection invalidating signal generating means A to invalidate the bus time-out detecting function provided for an input output controller C during the DMA transfer and an abnormality terminating signal generating means B to terminate to issue an abnormality terminating signal to terminate the transfer when the DMA transfer is an abnormal transfer. Thus, the next DMA transfer can be executed immediately after the preceding transfer is terminated by the time-out detection invalidating signal. |
