| 摘要 |
A computer aided logic design system for instantaneously compiling circuit component entries into a schematic model which provides immediate simulation of each entry or deletion into the electronic circuit schematic. The system includes software for processing logic designs which produces a signal table for storing all inputs and outputs of chips stored in a specification table. The processor also produces a call table that lists all chips from the chips specification table from which chip models can be retreived and executed. Additionally, a software routine produces a netlist transfer table that specifies the transfer of signals within the signal table produced by software processing, which correspond to the signal distribution in the circuit being designed. After production of the signal table, specification table, call table and netlist transfer table, a software processing routine executes sequential values retrieved from the call table and netlist transfer table to create a second signal table which is compared with the first signal table. The software processing routine continuous to execute values retrieved from the call table and netlist transfer table and compare the first and second signal tables until both the second signal table being created is identical with the first signal table stored in memory. The software processing means also includes a delay which delays sequential processing until the comparing step for comparing the second signal table with the first signal table reaches a stable state.
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