| 摘要 |
<p>PURPOSE:To read the data of a data width exceeding an output data width at high speed by fetching the data times as many as the number of the blocks of one output data width from a memory cell array address designated by a call means and outputting this data to an output part at high speed sequentially for every block by a data output means. CONSTITUTION:The data of 24 bits according to one address designation is realized by the data outputs of the three times D0-D7 based on the control signals S1-S3 of a counter 9. Therefore, after the output of the data of a sense amplifier 6x1, the data of a sense amplifier 6x3 is outputted at after 2T in time and since the time 2T is the two cycles of a clock phi, which is extremely short, the data of 24 bits can be outputted at high speed in the mask ROM of the data output of 8 bits. Thereby, according to the one address designation, the data of the data width obtained by integrating the output data width of an output part with the number of the blocks can be read at high speed.</p> |
