| 摘要 |
<p>PURPOSE:To decrease the clock attenuation and the deviation of the phase at each part of a clock signal line by providing a driver circuit for plural internal clock signal lines supplying a clock inputted from an external clock input terminal to an internal clock signal line and plural wires connecting external clock input terminal and the driver for the plural internal clock signal lines. CONSTITUTION:A clock signal given to an external clock input terminal 5 is given to wires 10, 11 via an input buffer 4. The clock given to the wire 10 is somewhat attenuated until being given to a driver circuit 1 and the phase is deviated. The phase of the clock inputted also to the wire 11 is deviated and the result is inputted to the driver circuit 2. In this case, since the wire length and width of the wires 10, 11 are substantially the same, the attenuation and phase shift of the clock due to the wire 10 and those by the wire 11 are identical. Since the clock is supplied to the clock signal line 8 by the two driver circuits, the attenuation and phase deviation of the clock at each part of the clock signal line 8 are very small.</p> |
