| 摘要 |
<p>PURPOSE: To allow one memory to conduct data rearrangement or signal processing by providing a 2nd shift register with a parallel input and a serial output and a 3rd address counter for rows. CONSTITUTION: First and second counters 2, 3 are used to control rows and columns independently of each other, data are written in a shift register 8 via a serial input 9 and transferred to a memory 1 and again transferred to the shift register 8 and the data are outputted from a serial output 10. A 2nd shift register 11 is connected to a memory 1 via an additive parallel input 12 and has a serial output 13 and uses a 3rd address counter 14 to control corresponding rows independently of the address counter 2. Thus, only one memory is enough to conduct rearrangement of serial image data or signal processing of the data.</p> |
