| 摘要 |
PURPOSE:To reduce the number of bits of the shift register of a correlator by thinning out the shift clock of the shift register and outputting only a specific part of a time-series signal as successive bits. CONSTITUTION:A control signal (m) goes up to a high level during a read period and a clock passed through AND gates 34 and 36 is inputted to clock converting circuits 30 and 31 and thinned out; and a clock with a doubled period, etc., is used as a shift clock to read time-series data DA and DB in A and B shift registers 70A and 70B of the correlator 7'. Then, when the signal (m) falls to a low level, the circulation of the registers 70A and 70B is controlled by a clock passed through AND gates 35 and 37 to generate a correlation signal (dx) through an exclusive OR circuit 74, etc. When the signal (dx) attains to a specific value close to a maximum value, the circuits 30 and 31 output successive clocks to form only a part including the center part of a time-series signal as successive bits, and the number of bits of the shift registers is reduced to shorten a processing time, improving the response characteristics. |
