| 摘要 |
The bias circuit is responsive to a voltage at a summing point where an input analog signal, an off set bias and an output analog signal from a D/A converter are added to each other. A successive approximation register is responsive to clock pulses and to the output signal from the comparator for producing a digital signal for the D/A converter. When the input analog signal amplitude is small, the reference voltage is shifted so that noises superposed on the voltage at the summing point do not cause the comparator to produce an erroneous output signal with which the state of the MSB is undesirably changed. As the amplitude increases, the reference voltage rises for ensuring sufficient dynamic range. |
