| 摘要 |
The adder with short delay time and few transistors comprises a couple of exclusive OR gates (XOR21-22) connected in series, AND gates (Nb, Nc), a NOR gate (Nd), and an inverter (Ne). The adding inputs (I1, I2) are provided to (XOR21) and the summed output (Sn) are provided from (XOR22). The carry signal (Cn-1) is provided to the input (I1*) of (XOR22) and the AND gate (Nb). The carry signal (Cn) is provided from the inverter (Ne).
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