| 摘要 |
The circuit for matching delayed data caused by clock delay between transmitter and receiver comprises a first counter (1) for counting input clock pulse, an address selector (2) of receiver for providing memory address and chip selecting signals, a memory (3) for accessing parallel voice data of receiver, an P/S data converter (4) for converting parallel voice to serial one, a coder/decoder (5) for converting the serial data to digital one, a S/P converter (6), a matching cct. (7) for matching the output of (6) with transmitting clock, and a load control cct. (8) for providing delayed output of the frame synch. bit.
|
