| 摘要 |
PURPOSE:To reduce chip area, by arranging a plurality of a first layer wiring segments having, on end-portions, contact holes connecting a first and a second wirings, in the manner in which said contact holes on the first layer wiring segment are arranged in a line along the main wiring direction of the second layer wiring. CONSTITUTION:Contact holes 2 on a first layer wiring segment 1 connect a first layer wiring and a second layer wiring, without distinguishing whether a plurality of the first layer wirings are in a basic cell region or in a wiring region. These contact holes are regularly arranged in a line along the main wiring direction 4 of the second layer wiring. Therefore, the wiring interval rule of the second layer wiring can be set identical, for the basic cell region and the wiring region. As a result, the second layer wiring formed in the wiring region can be extended into the basic cell region in a line without being bent in the midway, so that special regions to adjust the wiring interval rule are unnecessitated. Thereby reducing chip area. |
