发明名称 TIMING SWITCHING SYSTEM FOR TRANSMITTER
摘要 PURPOSE:To conduct efficient loopback test by storing information relating to a clock source of data transmission in a network so as to switch the synchronizing timing of data transmission based on the information. CONSTITUTION:A command signal from a MODEM 221 is synchronous with a clock source 223 and sent to a MODEM 251 via MODEMs 231, 241. In receiving the command signal sent from the MODEM 221, a main control section 321 reads clock source information stored in a clock information storage section 311 and changes the timing for the modulation implemented synchronously with a synchronizing signal 343 generated from an extracted clock signal 353 extracted by a demodulation section 351.
申请公布号 JPH01109842(A) 申请公布日期 1989.04.26
申请号 JP19870267101 申请日期 1987.10.22
申请人 FUJITSU LTD 发明人 MIZUTANI YASUNAO
分类号 H04L29/14;H04L7/00;H04L13/00 主分类号 H04L29/14
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