发明名称 PHASE LOCKET LOOP CIRCUIT
摘要 PURPOSE:To prevent out-of-synchronism of a phase locked loop circuit caused by missing signal by suppressing the fluctuation of the recovered clock during signal missing and suppressing the fluctuation of the recovered clock just after the recovery of signal missing. CONSTITUTION:A hold circuit 4 does not output a phase error signal given from a phase comparator 3 during missing of signal to a low-pass filter(LPF) 5 but outputs a holding voltage to the voltage LPF 5 by using a gate signal (b). That is, a voltage controlled oscillator (VCO) 6 generates a recovered clock by the DC voltage through the phase comparison just before missing of signal during the missing of a reference signal, then no fluctuation of recovered clock due to missing signal is not caused. Moreover, the phase comparator 3 applies phase comparison between a frequency division signal and a pseudo pulse (a) in place of the missing reference signal. Thus, the fluctuation of the recovered clock just after the recovery of signal missing is reduced. Then the out-of- synchronism caused by the missing signal is prevented.
申请公布号 JPH01108812(A) 申请公布日期 1989.04.26
申请号 JP19870263815 申请日期 1987.10.21
申请人 HITACHI LTD 发明人 FUNATO SHOICHIRO;HOSHINO TAKASHI;TAKEUCHI TAKASHI
分类号 H03L7/10;G11B20/10;H03L7/14 主分类号 H03L7/10
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