发明名称 MASTER SLICE SYSTEM SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To restrain the increase of chip area to a minimum, by setting the length of a first layer wiring having, on both ends, contact holes for connection with a second layer wiring, to a length necessary and sufficient to make two lines of the second layer wiring pass, and arranging said first layer wiring regularly on a master slice. CONSTITUTION:The first layer wiring 7, 11, 13 is provided, on both ends, with contact holes 9a, 9b, 15a-15d for connection with second layer wirings 6, 8, 10, 12, 14. The length of the first layer wiring is set to length necessary and sufficient to make pass two lines of second layer wiring 6, 8, 12, 14 which are kept, by an insulating film, electrically independent of the first layer wiring 7, 11, 13. Thus the first layer wiring segments of defined shape are constituted, which are regularly arranged on a master slice. Thereby shortening the time required for custom process after master slice process, and restraining the increase of chip area necessary for wiring.
申请公布号 JPH01109742(A) 申请公布日期 1989.04.26
申请号 JP19870267065 申请日期 1987.10.22
申请人 MATSUSHITA ELECTRON CORP 发明人 FUKUI YUUKO;OTANI KAZUHIRO;MIYAMOTO HIROYUKI;NISHIURA MASAO;CHIMURA MORIYUKI
分类号 H01L21/82;H01L21/3205;H01L23/52;H01L23/522;H01L23/528;H01L27/118 主分类号 H01L21/82
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