INTEGRATED WRITE-READ MEMORY

摘要

An integrated write/read memory consisting of a matrix of normal memory cells organized in rows and columns. The memory further includes a smaller matrix of redundant memory cells having their own column and row address decoders that can be engaged to replace any faulty memory cells in the normal matrix. The redundant address decoders are connected to all the address lines by means of fusible links so that any redundant address gate can be programmed to emulate the address of a faulty memory cell. The system further includes logic controls that automatically disables any normal memory address if a redundant memory cell is programmed to take its place.