| 摘要 |
PURPOSE:To execute the operation of a memory at a high speed by controlling a delay time of a delaying circuit by a detecting means for detecting a working variance of a process. CONSTITUTION:In an internal clock signal generating circuit PC, a detecting circuit CTR is a circuit for detecting a working variance of a process or a characteristic variance of an element such as a MOSFET, etc., generated by said variance, and by its output, a delay time of a delaying circuits DLY is controlled. Also, a driving circuit is constituted by cascading a CMOS inverter, etc. Accordingly, an increase portion of the delay time by the driving circuit is offset, and the dependency against a process working variance of the delay time which has added up the driving circuit part and the delaying circuit part DLY becomes small. In such a way, an operation speed of a memory array and the delay time of an internal clock signal can be brought to matching, and the operation of a memory can be executed at a high speed. |
