| 摘要 |
A field-oriented controller for a 3 phase induction motor is powered by a dc power source through a static inverter. Current reference signals are compared with current feedback to produce error signals. They are amplified by a proportional plus integral amplifier, whose output goes to a threshold comparator having negligible hysteresis. Flip-flops, through which the threshold comparators' gating signal outputs are fed, are clocked at a fixed frequency to introduce pseudo-randomness into the gating times. This reduces apparent acoustic noise of the motor. Asymmetrical anti-overlap delays for the gating signals are made long enough to serve also as the principal means for limiting the maximum frequency of gating. Locking circuitry overrides the proportional integral error signal in one phase at a time, and holds the inverter's gating in one switching state throughout the approximate middle 60 DEG interval of each phase. During each such 60 DEG locking interval, the integration capacitor of that phase's proportional plus integral error amplifier is short circuited to prevent motor current transients at the end of the interval. The locking circuitry is disabled at very low speeds.
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