| 摘要 |
Two logic circuits (4A, 4B) are utilized in alternation for controlling the processing of successive pixels that are detected to be erroneous. Each logic circuit has its own counter 5A and 5B for associating the undisturbed pixels with ordinal numbers designating their spacing from the disturbed pixel under processing and likewise has a separate PROM (6A, 6B) and a separate multiplier for weighting the undisturbed pixel values, as well as an accumulator (10A, 10B) for summing the weighted values to produce a substitute value, so that undisturbed pixels lying between two disturbed pixels can all be used, where necessary, both for compensating for a preceding disturbed pixel and a following disturbed pixel. When a following disturbed pixel is detected while a preceding disturbed pixel is being processed by a logic circuit, that logic circuit provides a special reset to its counter and accumulator and selects another PROM program in accordance with the shortening of the "filter length" by the nearness of the two disturbed pixels. When no defective pixels appear on the counters, multipliers and accumulators do not need to operate.
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