| 摘要 |
A semiconductor memory device is provided to select a word line more efficiently by receiving and decoding a row address. A first word line driving part(140A) comprises N unit driving circuits to drive N word lines arranged in a first cell block. A second word line driving part(140B) comprises N unit driving circuits to drive N word lines arranged in a second cell block. A common address latch part latches a first address to select one of M group driving circuits arranged in the first or the second word line driving part and outputs the latched first address to the first or the second word line driving part. A first address latch part(130A) receives a second address of Log2 N bits to select N word lines arranged in the first word line driving part and outputs the second address to the first word line driving part. A second address latch part(130B) receives the second address of Log2 N bits to select N word lines arranged in the second word line driving part and outputs the second address to the second word line driving part.
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