| 摘要 |
PURPOSE:To improve resistance for a software error by providing a memory cell capacity in a parity bit group larger than that in a normal bit group. CONSTITUTION:In the memory cell, MOS transistors T1-T4 are formed by a dispersing layer 1 and a polycrystal silicon layer 2 to constitute a word line formed on the dispersing layer. And the normal bit group and the parity bit group can be formed by using the memory cells, and the dispersing area of the memory cell capacity of the parity bit group is set larger than that of the memory cell capacity of the normal bit group. In such a way, it is possible to obtain the high resistance for the software error. |
