| 摘要 |
An address generator responsible to input parameters for generating addresses to read out the content of a memory along parallel lines disposed at an angle to the orthogonal rows and columns of storage elements. The address generator has a first pair of registers coupled by an adder to generate line corrected X addresses, a second pair of registers coupled by an adder for generating first address corrections, an adder summing said line corrected X addresses with said first address corrections to generate X addresses, a third pair of registers coupled by an adder to generate line corrected Y addresses, a fourth pair of registers coupled by an adder to generate second address corrections, and an adder summing said line corrected Y addresses with said second address corrections to generate Y addresses. |
