| 摘要 |
The invention relates to a timing recovery circuit. The circuit comprises means (11) for detecting the varying points of a split-phase signal having a pattern of the repetition of logical "1" and "0" at its beginning, voltage-controlled oscillator means (13), frequency dividing means (17), selector means (16), phase detector means (12), and control means (15) for controlling said selector means (16) so that it selects the output of said frequency dividing means (17) during said repetitive pattern of logical "1" and "0" and that of said voltage-controlled oscillator means (13) elsewhere. The timing recovery circuit permits ready largescale integration. |
