发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To shorten the tester pattern of a counter and to shorten the testing time of an n-bit counter by providing a circuit to divide the n-bit counter into m pieces of n/a bit counters and a circuit to mutually compare the outputs of respective corresponding bits. CONSTITUTION:A counters CNT1 and CNT2 are 4 bits binary counters, respectively, and by inputting the CRY signal of the CNT1 to the ENT terminal of the CNT2 at the time of inputting a low signal to a TEST terminal, they compose 8 bits binary counters. At the time of detecting a trouble, a High signal is inputted to the TEST terminal, a dividing circuit 1 is operated, and the two independent 4 bits binary counters CNT1 and CNT2 are made. A CLOCK signal is inputted, and the CNT1 and CNT2 are operated. At such a time, the outputs of respective corresponding bits of the 4 bits binary counters of the CNT1 and CNT2 are mutually compared by a comparing circuit 2. When the result coincides, the high signal is outputted to a COUT terminal, and the Low signal is outputted to the COUT terminal at the time of a nun-coincidence.
申请公布号 JPH01101024(A) 申请公布日期 1989.04.19
申请号 JP19870259027 申请日期 1987.10.13
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 ONO TERUSHI
分类号 H01L21/66;G05B23/02;H01L21/822;H01L27/04;H03K21/00;H03K21/40 主分类号 H01L21/66
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