| 摘要 |
<p>A digital frequency up conversion arrangement comprising a source of fixed high speed clock pulses the frequency of which is near to the desired output frequency of the converter arrangement, a high frequency counter (20) to which the clock pulses are applied to produce a repetitive fixed m-bit digital word in parallel output form, the sample rate of the m-bit word being equal to the high speed clock frequency, divider (21) to which the high speed clock pulses are applied to form a slow clock pulse train, a slow frequency NCO (22) to which the slow clock train is applied together with frequency control signals to produce m-bit words the sample rate of which is equal to the slow clock frequency, summing means (23) to which the high sample rate and slow sample rate m-bit words are applied to produce resultant m-bit words which form a digital representation of a sine wave at the required output frequency, and digital-to-analogue conversion means (25) to which the resultant m-bit words are applied to produce an analogue sine wave at the required output frequency.</p> |
