| 摘要 |
PURPOSE:To save time required for an evaluation test by providing a cell row marking in the vicinity of a plurality of basic rows of cells to identify each such basic row of cells. CONSTITUTION:A plurality of rows 2 of basic cells where a plurality of basic cells 21 formed based on an automatic layout design are arranged, and a wiring 3 connecting between the basic cells 2 as well as between the rows 2 of such basic cells to allow them to assume certain functions is provided, both on a semiconductor substrate 1. A cell row marking 4 is provided at the left side of each row 2 of the basic cells on the substrate 1 to identify each such row 2 of basic cells. These cell row markings 4 are generated upon the automatic layout design, and are allowed to be generated upon formation of the rows 2 of the basic cells, the wiring 3, etc. This allows each row 2 of the basic cells to be identified easily at the time of evaluation tests, thereby contributing to save time required for such evaluation tests. |
