| 摘要 |
<p>PURPOSE:To attain synchronization without adding external processing by temporarily stopping the dividing action of one divider, and obtaining synchronization with the start of the dividing action again when the dividing output of a basic clock from plural circuit systems is at an opposite phase. CONSTITUTION:When a 2-dividing output from circuit systems 1 and 2 is at the opposite phase, an FF4 fetches the 2-dividing output '1' from the circuit system 2 at the time of the fall of the basic clock, an FF5 fetches '1' from the FF4 at the time of the rise of the 2-dividing output from the circuit system 1, sends it to an OR gate 7, and '1' is outputted to a reset input terminal R of the circuit 2. Further, an FF6 fetches '1' from the FF5 at the time of the fall of the 2-dividing output from the circuit system 1, sends it to the OR gate 7, outputs '1' to the reset terminal R of the circuit system 2 until the FF6 outputs '1', stops the divider in the circuit system 2, and re-starts the dividing action in response to the pulse generating timing of the 2-dividing output of the circuit system 1.</p> |
