发明名称 エピタキシャルウエハの製造方法及び半導体装置の製造方法
摘要 <P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a high quality epitaxial wafer with reduced crystal defects and a sufficiently large carrier time constant, and to provide a method of manufacturing a semiconductor device using the epitaxial wafer. <P>SOLUTION: A method of manufacturing an epitaxial wafer comprises the steps of: (a) forming an epitaxial layer 13 having an impurity concentration of 1&times;10<SP POS="POST">14</SP>cm<SP POS="POST">-3</SP>or more to 1&times;10<SP POS="POST">16</SP>cm<SP POS="POST">-3</SP>or less on an SiC substrate 12 having an impurity concentration of 3&times;10<SP POS="POST">18</SP>cm<SP POS="POST">-3</SP>by epitaxial growth; and (b) consecutively removing the whole of the SiC substrate 12 and part of the epitaxial layer 13 from the side of the SiC substrate 12 having a structure obtained by the step (a) while leaving a predetermined thickness of the epitaxial layer 13. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP5921089(B2) 申请公布日期 2016.05.24
申请号 JP20110123158 申请日期 2011.06.01
申请人 三菱電機株式会社 发明人 大塚 健一
分类号 H01L21/20;H01L21/205;H01L21/265;H01L21/329;H01L21/336;H01L29/12;H01L29/739;H01L29/78;H01L29/861;H01L29/868 主分类号 H01L21/20
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