| 摘要 |
PURPOSE:To effectively execute the extension accuracy dividing instruction at high speed by extending a divisor register and a partial residual register with the data width of a dividing circuit. CONSTITUTION:In a dividing circuit composed of a divisor register 1', a multiple generating circuit 2 of the divisor, an adder 3, a partial quotient predicting device 4, a partial quotient generating part 5 and a partial residual register 6', only the divisor register 1' and the partial residual register 6' are extended by the data width of the dividing circuit, the divisor register 1' is extended to a high-order side 1a' and a low-order side 1b' and the partial residual register 6' is also extended to a high-order side 6a' and to a low-order side 6b'. Other arithmetic circuit is used by a time division appropriately. Thus, without expanding the data width of a high base non-recovering type dividing circuit, an extension accuracy dividing instruction can be executed effectively at high speed. |
