| 摘要 |
PURPOSE:To shorten a delaying time by providing plural selectors to select and output one of input data in accordance with a selecting control signal. CONSTITUTION:Serial data D of four-bit constitution added to an input terminal 11 are converted to parallel data in a serial/parallel converting circuit 9. Selectors 1-4 are the ones to select and output one of the data added to input terminals 11-15 in accordance with selecting control signals S1-S4. Selecting control signals S1-S4 outputted from ROM 5-8 and signals A3-A1 added as a reading address to the ROM 5-8 have the prescribed relation. A parallel/ serial converting circuit 10 executes the parallel/serial conversion of the data of the selectors 1-4 and outputs the serial data to an output terminal 12. Thus, the input data can be shifted by the delaying time for a selector one step and therefore, the delaying time can be shortened. |
