发明名称 STORAGE DEVICE
摘要 PURPOSE:To improve a check efficiency, by adding a partial write flag reset means and changing a normality check from a parity bit into an error correction code, when a readout request or a full write request takes place even if the partial write request is generated and the normality check with the parity bit is performed. CONSTITUTION:Data D0-D7 and parity bits P0-P7 are transmitted to a write register 205 from a processor 1000 via a data register 201 and a signal line 201. A hamming producing circuit 203 transmits its output to the write register 205 as a hamming code H. A normal write indicating discrimination circuit 204 decodes a request code transmitted from the processor 1000 via a request code register 202 and sets its output to the write register 205 as ''0'' level when the normal write and as ''1'' level when the partial write, as a partial write flag PW. Then, when the partial write is performed, the partial write flag PW is set, and when the normal write is performed, the partial write flag PW is reset.
申请公布号 JPS5919300(A) 申请公布日期 1984.01.31
申请号 JP19820128458 申请日期 1982.07.23
申请人 NIPPON DENKI KK 发明人 ISHIKAWA ITARU
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
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