Broadband multiple bit rate switching maxtrix for connection network

摘要

The matrix includes n mesh circuits CM1 to CMn each connected to an incoming mesh E1 to En, a spatial matrix MS of type n x m connected by incoming lines I1 to In to the mesh circuits, and to m outgoing meshes Z1 to Zm, and a control logic circuit CLC connected to each mesh circuit, and to an input address register, an output address register and an enabling input of the spatial matrix. Each mesh circuit comprises a spatial sub-mesh 8 for the high bit rate traffic and a temporal sub-mesh mt for the traffic of asynchronous temporal frames, of all-bit-rate channels.