| 摘要 |
<p>PURPOSE:To eliminate skew between output signals caused by the difference of wiring length between standard clock signals and to enable high speed operation of parallel processor system by arranging logic gates on the inside of a semiconductor chip in a circular arc centering around a chip corner or one point of a circumference side of a chip. CONSTITUTION:Logic gates 2 in the inside of a chip 1 are arranged in a circular arc centering around a corner of the chip 1 or one point of a circumference side of a chip 1. If a standard clock signal is supplied from the center 5 of the arc, each clock wiring 4 to the logic gate 2 of each signal line such as a flip-flop is distributed at a same distance. Accordingly, skew between signals of parallel output can be eliminated theoretically thus providing a system which can be operated at a high speed.</p> |
