发明名称 PARALLEL MULTIPLIER
摘要 PURPOSE:To prevent malfunction due to a level lowering by providing a depression type N-channel MOS transistor as a load element between a common output edge and a power source potential supplying terminal. CONSTITUTION:When any one of the four number of transmission gates 41-44 is selected according to the potential condition of a selection control signal lines 281-284, any one of multiplied number digit data Xi, inverting Xi, Xi-1, inverting Xi-1, which are correspondent to the selected transmission gate, goes to be an added number input Xin of a full-adder 10. Namely, the multiplied number data are shifted to a high order only for one bit. Thus, when any one of the gates 41-44 is selected and the selected gate transfers one level, a depression type N-channel MOS transistor 50 is operated as a load in a power source VDD side. Thus, the threshold of the transistor can be compensated and the potential of a common connecting point N can be caused to rise up to the VDD, namely, up to one level.
申请公布号 JPH0195328(A) 申请公布日期 1989.04.13
申请号 JP19870252855 申请日期 1987.10.07
申请人 TOSHIBA CORP;TOSHIBA MICRO COMPUT ENG CORP 发明人 SAKAGAMI KENJI
分类号 G06F7/53;G06F7/506;G06F7/508;G06F7/52;G06F7/533 主分类号 G06F7/53
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