| 摘要 |
A circuit arrangement is known for error detection in coded digital signals by means of checking the running digital sum with the aid of a differential amplifier connected as an integrator. A load impedance is situated in each case in the output circuit of the differential amplifier. The base-emitter diodes of transistors are used as triggers. This circuit arrangement is, however, not suitable for all signals which can be monitored by checking the RDS. The circuit arrangement proposed by the invention can be used to process all digital signals which can be monitored by checking the running digital sum. For this purpose, an integral controller is connected in parallel with each load impedance. The invention is applied, for example, in code protocol violation checking of CMI-coded data signals.
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