| 摘要 |
PURPOSE:To rapidly recover the stoppage time of a system by holding the power source turning-off signal of a processor in an access with an FF and inputting the signal to a next priority processor with an interruption circuit. CONSTITUTION:From processors A1a and B2b at units 1 and 2 sides, simultane ously, a reading writing request is issued, and when a bus arbiter 4 selects the request of a processor 1a, a bus using right is added to the processor 1a and a two-port memory 5 is accessed. When a power source circuit A16 generates the power source decrease during the memory access, a memory 5 is backed up by a back-up power source circuit 6 of a unit B. Next, the reading or right cycle of the processor 1a is forcibly completed by a control circuit 7, the bus arbiter 4 is released, and the reading or writing cycle from a processor 2a side is executed. A power source decrease signal is held at an FF11 and interruption is applied through an interruption circuit 2c to the processor 2a and the FF11 is reset. |
