| 摘要 |
<p>A synchronizing circuit using a D-type flip-flop 1 for synchronizing an asynchronous input signal (o0) with a clock pulse can be in a metastable or logically undetermined state when the transition of the state of the input signal coincides with the rise of the clock pulse. For preventing such metastability the synchronizing circuit comprises means to prevent the supply of the input signal to the flip-flop during the state of transition of the clock signal. These means preferably include gate means (10,12) for supplying the input signal and the complementary thereof as set and reset signals, respectively, to a Set-Reset-Flip-Flop 8, whose output is supplied to the flip-flop 1 as the input signal, said gate means (10,12) being controlled by a control signal obtained by delaying the clock pulse.</p> |
