| 摘要 |
<p>PURPOSE:To optimize a precharge time and a discharge time by generating a control signal for a ROM from the state of an output line that discharges a potential set by precharging in another potential at every reading. CONSTITUTION:At the timing of the rise of a read signal, a signal phiAS comes in L, the P-MOS of a word line precharge PCh circuit 102 turns on, and all the word lines are made PCh. A signal phiMS also comes in L simultaneously, the P-MOS of a memory data output line charge circuit 101 also turns on, and output lines are made PCh. Accordingly, an EN signal comes in an H-level, and a control circuit 107 makes the phiAS in H to release the PCh state of the word lines. One piece of word line selected by an address recorder 103 is connected to a GND electrode, and its charges are discharged, and it comes in L. The circuit 107 shifts the phiMS to H at the timing of rising of the EN signal to turn off the P-MOS of the circuit 102. A discharge sensing circuit 109 makes a WAIT signal in L upon completion of a discharge to inform the fulfilment of a ROM output.</p> |
