| 摘要 |
PURPOSE:To repeatedly achieve parallel/serial conversions with arbitrary bit lengths without being limited the total number of latch circuits by adding a shift control circuit that selects two data. CONSTITUTION:When a shift control signal (c) is in H, an output data from an (x-1)-stage latch circuit A(x-1) is inputted to the data input terminal 1 of an x-stage latch circuit Ax. Accordingly, in this case, a normal shift action is achieved. However, since a serial data output signal (b) is fed back to a first-stage latch circuit 1, the data is rotated. Assuming that the total number of the latch circuits is (n), the signal (b) returns to its original value when a shift clock signal is inputted N-times. Next, when the signal (c) is made in L, an output signal (b) from the final-stage latch circuit An is fed back to the circuit Ax, and the data loaded from the Ax to the An is rotated. |
