High-speed, high-drive output buffer circuits with reduced ground bounce

摘要

A high-speed, high-drive output buffer circuit for providing an output signal at an output node with reduced ground bounce includes an AC buffer (12) and a DC buffer (14). The AC buffer (12) is formed of a first pull-up transistors (Q1) and a first pull-down transistor (Q2) connected in series and is responsive to a data input signal for generating quickly high-to-low and low-to-high transitions at the output node. The DC (14) buffer is formed of a second pull-up transistor (Q3) and a second pull-down transistor (Q4) connected in series and is responsive to the data input signal for generating slowly high-to-low and low-to-high transitions at the output node. The second pull-up transistor (Q3) is delayed in its turn-on with respect to the turn-on of the first pull-up transistor (Q1) when the output node is making the low-to-high transition so as to reduce the ground bounce. Similarly, the second pull-down transistor (Q4) is delayed in its turn-on with respect to the turn-on of said first pull-down transistor (Q2) when the output node is making the high-to-low transition so as to reduce the ground bounce.