发明名称 |
Arithmetic and logic unit with prior state dependent logic operations |
摘要 |
The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of instruction steps. The arithmetic and logic unit of the present invention has a control portion provided with a control circuit for performing the specified operation such as operation of MAD by a small number of instruction steps.
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申请公布号 |
US4821225(A) |
申请公布日期 |
1989.04.11 |
申请号 |
US19870042532 |
申请日期 |
1987.04.27 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ANDO, HIDEKI;MACHIDA, HIROHISA |
分类号 |
G06F7/00;G06F7/575;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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