| 摘要 |
A manufacturing process and structure of a semiconductor memory device especially a Dynamic Random Access Memory (DRAM), each memory cell of which comprises one transistor and one capacitor. The process comprises the steps of (a) selectively forming an insulating layer on a semiconductor substrate; (b) forming a semiconductor layer on the insulating layer, the semiconductor layer being connected to the semiconductor substrate via the insulating layer; (c) forming a protective layer on the semiconductor layer; (d) forming a window having a predetermined width through the protective layer at a position of the protective layer offset from an end of the insulating layer and forming a trench through the window with the insulating layer and protective layer serving as masks so that the semiconductor layer is still connected to the semiconductor substrate via the end of the insulating layer; and (e) forming the capacitor in the trench with the transistor formed in the semiconductor layer. Both transistor and capacitor are connected to a region of the semiconductor substrate adjacent to a side wall of the insulating layer. In addition, another transistor of the adjacent memory cell is separated from the capacitor with the insulating layer located below the transistor.
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