发明名称 |
Semiconductor memory device having data bus reset circuit |
摘要 |
A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.
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申请公布号 |
US4821232(A) |
申请公布日期 |
1989.04.11 |
申请号 |
US19870097556 |
申请日期 |
1987.09.16 |
申请人 |
FUJITSU LIMITED;FUJITSU VLSI LIMITED |
发明人 |
NAKANO, MASAO;OHIRA, TSUYOSHI;MOCHIZUKI, HIROHIKO;KODAMA, YUKINORI;NOMURA, HIDENORI |
分类号 |
G11C11/409;G11C7/10;G11C7/20;(IPC1-7):G11C13/00;G11C11/40 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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