发明名称 Semiconductor memory device having test pattern generating circuit
摘要 A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit; an element for receiving external signals supplied from the outside; and an input switching circuit connected between the test pattern generating circuit and the receiving element, for switching the input supplied to the internal circuit between output signals generating from the test pattern generating circuit and the external signals, the output signals generated from the test pattern generated circuit being input to the internal circuit through the input switching circuit in a test mode, the external signals being input to the internal circuit through the input switching circuit in a usual mode; the test pattern generating circuit, the input switching circuit, and the internal circuit being provided on the same chip.
申请公布号 US4821238(A) 申请公布日期 1989.04.11
申请号 US19860895091 申请日期 1986.08.11
申请人 FUJITSU LIMITED 发明人 TATEMATSU, TAKEO
分类号 G11C29/00;G11C29/06;G11C29/36;(IPC1-7):G11C7/00 主分类号 G11C29/00
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