| 摘要 |
A clock signal multiplexer for combining a plurality n of input clock signals of the same frequency but differing phases into a single channel, by selectively passing one of the n input clock signals to an output of the multiplexer to the exclusion of the other n-1 input clock signals, includes n input circuits to each of which a respective one of the n input signals is supplied together with a respective clock enable signal, a logic circuit coupling the input circuits to a signal synchronizer, the logic circuit operating to enable said signal synchronizer in respect of the input clock signal corresponding to that one of the n clock enable signals which is in a select condition, and further operating on return of the one of said clock enable signals to a non-select condition and transition of another of the clock signals to the select condition to disable the signal synchronizer in respect of the previously selected input clock signal, and to enable the signal synchronizer in respect of the input clock signal corresponding to the other clock enable signal, a clock signal selector to which the input clock signals are supplied and to which the signal synchronizer is connected, the signal synchronizer enabling the clock signal selector to pass the enabled input clock signal to the output of the multiplexer via a clock regenerator.
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