发明名称 ENCODER, DECODER AND METHOD
摘要 FIELD: information technology.SUBSTANCE: codec (30) includes at least one coder (10) and at least one decoder (20). Encoder includes data processing circuit for application to input data (D1) of one of forms of differential and/or summing coding to form one or more corresponding coded sequences, which is subjected to cyclic shift relative to maximum value and/or cyclic shift relative to minimum value to generate encoded output data (D2 or D3). Decoder includes data processing circuit for processing one or more parts of encoded data (D2 or D3) configured to use one of difference and/or summing decoding types to one or more corresponding coded sequences specified one or more parts, wherein one or more encoded sequences are subjected to cyclic transition operation relative to maximum value and/or cyclic transition relative to minimum value for formation of decoded output data (D5).EFFECT: high degree of data compression.44 cl, 3 dwg, 2 tbl
申请公布号 RU2595916(C1) 申请公布日期 2016.08.27
申请号 RU20150132041 申请日期 2014.02.27
申请人 Gurulodzhik Mikrosistems Oj 发明人 KALEVO Ossi
分类号 H03M7/32;H03M7/36 主分类号 H03M7/32
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