| 摘要 |
PURPOSE: To attain the high speed operation of a continuous approximate register by providing a data latch and a related gate circuit, and escaping inside competition by delaying transmission. CONSTITUTION: Continuous approximate comparator data are inputted to a terminal 6, and inputted prescribed data latches 11-1-11-N according to each level. Also, when a prescribed logical output level VDD is inputted to a shift register bit 13-1, and a signal clock inputted to a terminal 15 is inputted to bits 13-1-13-N, the output is inputted to the L terminal of the corresponding latch 11. The latch 11 delays the inputted data, and the data are outputted and inputted to a corresponding AND gate 12(12-1-12-N) with the input of the terminal L. Here, the output of the bit 13-1 is repeated until the N pieces of bits 13 are forwarded, and it reaches the bit 13-N. As a result, the exact continuous approximation with a smaller number of approximation than an input signal VIN can be obtained. The gate 12 is provided with an FF circuit function, and the delayed data are outputted through a terminal 8. As a result, inside competition can be escaped, and the number of approximation can be decreased. Thus, the high speed operation of a continuous approximate register 7 can be attained. |
