发明名称 MULTI-FRAME SYNCHRONIZATION DETECTION CIRCUIT
摘要 PURPOSE:To cope with a change in a formed frame and to attain the establishment of synchronization in a prescribed time by storing a word length of a synchronizing signal of a reception signal extracted at the interval of occurrence of a synchronizing signal as one word and comparing the word with a synchronizing signal pattern. CONSTITUTION:A counter 13 counts a bit synchronizing signal and gives an address to a storage circuit 7 and the count is circulated at 0-771 and a carry signal is given to a counter 15 at the circulation. The counter 15 counts the carry signal and is circulated by 0-5. A counter 17 counts the carry signal of the counter 15. An arithmetic circuit 5 processes the counters 15, 17 and a reception signal, etc., to read/write the signal to the circuit 7. The circuit 7 stores the signal processed by the circuit 5 according to the address sent from the counter 15 via the counter 13 and the circuit 5. A comparator 9 compares the signal outputted from the circuit 5 with the signal pattern of the multi-frame synchronizing signal stored in advance to detect the multi-frame synchronizing signal.
申请公布号 JPS6490631(A) 申请公布日期 1989.04.07
申请号 JP19870247515 申请日期 1987.09.30
申请人 TOSHIBA CORP 发明人 ASANO ATSUSHI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
代理机构 代理人
主权项
地址