Data converter and image reader using the same.

摘要

A data converter is provided with a parallelly arranged shift registers (SR0 - SR7) each having a plurality of bits of storage capacity. A counter (32) counts clock pulses and supplies its counter output to a decoder (31), which in turn supplies loading pulses (LP) to the respective shift registers. The shift registers parallelly input a plurality of bit-serial data in response to the loading pulses and internally transfer the storage contents bit by bit in response to transfer signals (RP), so that the data read from the shift registers are outputted through an output control gate (33).