| 摘要 |
PURPOSE:To be adapted to various pieces of equipment with a transmission speed and to prevent the same data from being superimposed and sampled by preventing the transmitting of a data writing signal and reproducing from output data at a receiving side. CONSTITUTION:A data writing signal(WD signal) inputted incidental to the input data is detected by a WD signal detecting circuit 62 and a parallel serial converting timing signal PS is outputted to a parallel serial converting circuit 61. A serial signal demodulated suitably by a receiving circuit 56 is inputted to a serial parallel converting circuit 64. A serial signal detecting circuit 65 detects the arrival start of the serial signal, triggering is executed to a serial parallel converting timing generating circuit 66, only the number of the bits of data is counted for the shift clock pulse of the serial signal and a data receiving completing signal DE is generated. A delaying circuit 67 delays only for a prescribed time and outputs as a reproducing WD signal to the equipment side. Thus, the input data are not superimposed and sampled. |
