发明名称 SYNCHRONIZATION DECIDING CIRCUIT FOR PHASE CONTROL LOOP
摘要 PURPOSE:To attain the secure and stable synchronization decision without using an analog circuit by specifying the action of a counting means to execute the frequency-dividing action at the same period as the synchronizing signal based on a phase difference signal from a phase comparator and deciding with the counted value of the counting means. CONSTITUTION:For a phase comparator 32, when a phase error occurs at the signal of input terminals R and V, either of output terminals U1 and D1 goes to an 'L' level and when the phase error eliminated, both go to an 'H' level. A signal UD1, in which signals U1 and D1 and obtained through an AND gate 33, is made into the enable signal of a horizontal counter 34. In a phase locked condition, the signal UD1 becomes the 'H' level, the counter 34 becomes the enable and always, the stepping of the counting is executed. When the counted value exceeds the threshold at a 1H period and the time constant of a mono- stable mono-multi vibrator 38 is set to 1H or above, the output continues to always go to the 'H' and is decided to be the phase locked condition. The threshold of comparators 35 and 36 is made into S1, S2 (S1>S2), and at the time of no phase locking, a comparator 35 is selected and at the time of phase locking, 36 is selected.
申请公布号 JPS6489717(A) 申请公布日期 1989.04.04
申请号 JP19870244043 申请日期 1987.09.30
申请人 TOSHIBA CORP;TOSHIBA AUDIO VIDEO ENG CORP 发明人 IKEGAMI KIYOSHI;ISHIKAWA TATSUYA
分类号 H03L7/095;H03L7/08 主分类号 H03L7/095
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