发明名称 Microprocessor with an interruptable bus cycle
摘要 In a semiconductor integrated circuit, an internal logic circuit outputs information for an external bus via buffer circuits. The output of the buffer circuit is placed in a high impedance state by responding to a control signal, and the information which is output from the internal logic circuit to the buffer circuits is held in the bus cycle during which the control signal is input. In the response to a release of the control signal by the input of the control signal, the interrupted bus cycle is released, and the information stored is output via the buffer circuit to the external bus.
申请公布号 US4819158(A) 申请公布日期 1989.04.04
申请号 US19850739338 申请日期 1985.05.30
申请人 FUJITSU LIMITED 发明人 MIYASHITA, TAKUMI
分类号 G06F13/36;G06F12/00;G06F13/16;G06F13/18;G06F13/20;G06F13/28;G06F13/30;G06F13/364;(IPC1-7):G06F1/00 主分类号 G06F13/36
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